Low power semiconductor circuit designs have become increasingly useful in the last few years as more wireless battery operated products, and similar products, have been developed which require short bursts of very fast operation, separated by long `sleep` periods during which the semiconductor circuits are expected to draw minimal power. An additional significant requirement for such applications is a very fast wake up time for the system when an external event wakes up the system.
In order to meet these requirements, special circuitry must be implemented in the circuit.
In order to achieve the very low power consumption requirement during the `sleep` periods or low power mode, low power circuits are normally clocked with an external low frequency 32 KHz crystal and an internal oscillator and Phase Lock Loop (PLL) provide an accurate system clock with a high frequency. In the low power mode, the PLL is disabled internally or both the PLL and the oscillator are disabled internally.
When the PLL alone is disabled, the power consumption is in the order of milli-watts and the wake up time is in the order of milli-seconds (about 15.6 msecs using a 32 KHz crystal). When both the PLL and the oscillator are disabled, power consumption is in the order of micro-watts but the wake up time of the oscillator is measured in seconds (about 2.2 seconds using a 2 KHz crystal).
There is therefore a need for an improved clock system for generating a system clock signal that has both a low power consumption in the low power mode and a fast wake up time.